TSMC Expands CCD and LCOS Foundry Processes

TSMC Expands CCD and LCOS Foundry Processes

11.18.2002

Earlier this year, semiconductor contract manufacturer Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) (Hsinchu, Taiwan) (www.tsmc.com) outlined its "multimedia and interface technology" roadmap to enable a new class of chips for flat-panel displays, liquidcrystalonsilicon (LCOS) microdisplays and other products. The company plans a bold and aggressive move to 90-nm (0.09-micron) process technology, as well as new moves in its high-voltage IC capability.

The high-voltage IC processes are needed for LCD and plasma panel drivers, as well as LCOS backplanes.

Currently, TSMC offers its CMOS DDD and LDD technologies. For LCOS backplanes, either the 0.35-micron LDD 3.3V/5V process or the 0.35-micron DDD 3.3V/12V process can be used. The most advanced DDD process is a 0.35-micron 3.3V/12V technology, while the LDD process can offer 3.3V/40V capabilities using a 0.5-micron geometry.

By year end, plans call for the establishment of a new 3.3V/18V, 0.35-micron DDD process. For early 2004, a 0.25-micron process will be ready with 2.5V logic and higher voltage support still TBD, but 8V looks like an initial target.

On the LDD front, TSMC will offer 5V/100V, 1-micron and 3.3V/40V, 0.35-processes by year end. And, in 2004, it will establish 0.25-micron processing offering 2.5V/3.3V and 2.5V/8V capabilities.

TSMC already has several customers for LCOS backplane fabrication including eLCOS (San Jose, CA) (www.elcos.com). "The LCOS microdisplay has potential as a cost-effective large-screen display technology for HDTV, so we think it is a important candidate for 0.35/0.25-micron capacity loading," says TSMC sr. director CC Tsai. "Loading in 2004 will depend on how successful our customers' products are in the market."

TSMC also has a good business in CCD imagers using its 0.5 to 0.25-micron processes on 6- and 8-inch wafers. By year end, TSMC will offer a 0.18-micron CCD image sensor process based on a new six-layer metal technology that will enable 1.8V/3.3V chips with a pixel size of 3 x 3-micron and 3 megapixels of resolution.

TSMC, CC Tsai, [886] 3-666 5944, cctsai@tsmc.com.tw

Excerpted from the Projection Supply Chain Report--Autumn 2002